Abstract

Network processors generated huge excitement, interest and investment in the late 90's and into 2000, promising to replace fixed-function ASIC chips in networking equipment by high-performance programmable devices. The sheer performance requirements of these devices led to a flurry of activity in both processor architecture, software and especially the interaction between architecture and software, with many diverse approaches competing for survival. The subsequent collapse of the market for communications equipment hit network processors hard.

This talk will give a progress report on network processors and embedded network processing elements. We begin by describing the application requirements for these computing devices and outline some of the processing tasks required – packet reassembly, classification, policing, statistics, state management, packet modification, queuing, scheduling and traffic shaping, buffer management, and packet segmentation – and their memory and I/O needs. We will then discuss how these requirements impact processor architecture, programming models and languages, and partitioning between software and hardware functionality, drawing examples from several of the network processor survivors. We will conclude with a market outlook for network processors, the impact that will likely have on future developments, and open research problems.